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課程名稱 |
系統晶片驗證
SOC VERIFICATION |
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開課學期 |
98-2 |
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授課對象 |
電機資訊學院 電機工程學研究所 |
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授課教師 |
黃鐘揚 |
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課號 |
EEE5023 |
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課程識別碼 |
943 U0250 |
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班次 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
選修 |
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上課時間 |
星期五2,3,4(9:10~12:10) |
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上課地點 |
電二104 |
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備註 |
總人數上限：50人 |
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課程網頁 |
http://cc.ee.ntu.edu.tw/~ric/teaching/SoC_Verification/S10/ |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
1.VERIFICATION PROBLEMS IN SOC DESIGNS.
2.BLOCK, SYSTEM, VS. SOC VERIFICATION.
3.SIMULATION-BASED VERIFICATION. TESTBENCH AUTHORING.
4.ASSERTION-BASED VERIFICATION (ABV). PROPERTY SPECIFICATION LANGUAGE.
5.SIMULATION SPEED-UP BY EMULATION. PROTOTYPING VERIFICATION.
6.FORMAL VERIFICATION TECHNIQUES. AUTOMATIC TEST PATTERN GENERATION (ATPG). BOOLEAN SATISFIABILITY (SAT). BINARY DECISION DIAGRAM (BDD).
7.SEMI-FORMAL VERIFICATION.
8.EQUIVALENCE CHECKING. PROPERTY CHECKING.
9.FUTURE SOC VERIFICATION CHALLENGES AND DIRECTIONS.
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課程目標 |
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課程要求 |
1.Homework 30%
2.Mid-term exam 30%
3.Final exam or project 40%
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預期每週課後學習時數 |
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Office Hours |
另約時間 |
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指定閱讀 |
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參考書目 |
1.“SYSTEM-ON-A-CHIP VERIFICATION - METHODOLOGY AND TECHNIQUES”, PRAKASH RASHINKAR, PETER PATERSON, AND LEENA SINGH, KLUWER ACADEMIC PUBLISHERS.
2.“ASSERTION-BASED DESIGN”, HARRY FOSTER, ADAM KROLNIK, AND DAVID LACEY, KLUWER ACADEMIC PUBLISHERS.
3.“WRITING TESTBENCHES: FUNCTIONAL VERIFICATION OF HDL MODELS”, JANICK BERGERON, KLUWER ACADEMIC PUBLISHERS.
4.CLASS HANDOUTS/SLIDES.
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評量方式
(僅供參考) |
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